Excessive clock jitter is a big problem the DAC. It is mainly from using a so-called PLL (Phase Locked Loop) circuit to extract the clock embedded within the SPDIF signal.
Jitter is best described as “the right data/signal level at the wrong time”. Digital data via SPDIF is commonly received 100% accurate, fully bit-perfect. However Jitter will introduce measurable and in sufficient amounts, audible distortion even with the perfect digital data.
This example below shows how the decoded signal compared to the original source signal is different due to cable-induced jitter:
Jitter caused by Bad Clock
With more time, one may wish to explore: http://en.wikipedia.org/wiki/Jitter
SPDIF’s analogue transmission roots…
The SPDIF Signal specification is a direct result of the late 70’s crossover between Video and Digital Audio Technology, where video recorders were used to record digital audio embedded in a video signal, which is actually what SPDIF in essence represents.
Once adopted as the de facto solution to transmit digital audio between Transport & DAC, a solution was needed to extract the clock from the SPDIF data-stream, commonly adopted is a so-called Phase Locked Loop (PLL).
…that led to PLL, a widely-accepted but flawed 'solution'
A PLL is an essentially analogue system with an analogue filter response that controls the DAC's clock and attempts to keep it synchronised with the source. Jitter from the source is filtered using the analogue filter, which is usually set at a very high frequency (around 20kHz or higher in common SPDIF receivers ).
Some DACs have attempted to reduce the problem by adding a second PLL. Most, simply choose to ignore the issue entirely. A secondary PLL will filter source jitter from a frequency much lower than 20kHz, often as low as 100’s Hz. However, as the filter slope is not very steep (usually jitter is doubled with every halving of frequency), some jitter must always pass the filter. A secondary PLL, no matter what its cut-off frequency for filtering jitter, is merely a poorly conceived analogue band-aid on top of the same.
1The Crystal CS series, TI DIR series and AKM AK series etc
The key issue is that an analogue system is used to solve what is essentially a purely digital problem, namely that of controlling the flow of data between source and DAC. Most worrying is that the use of PLL’s, and mostly only a single PLL as well, has become the industry standard.
To overcome this essentially digital problem, AMR not surprisingly, has developed a purely digital solution without any analogue circuitry, analogue filters, PLL circuits etc.
AMR’s digital solution to a digital problem
AMR's solution is the Zero Jitter Mode, which is a combination of an Intelligent Memory System (IMS) and our unique Global Master Timing (GMT) clock system.
- Intelligent Memory System (IMS)
The IMS holds a large number of complete audio samples, so it can absorb quite a large amount of source clock variation (jitter, drift) in the incoming signal, while still sending out data at a fixed clock rate, regardless of the variation of the incoming clock. The IMS is not a simple FIFO memory buffer.
- Global Master Timing (GMT)
The GMT System is not a secondary PLL, instead it is an entirely new concept. GMT is a system that will completely block jitter from the source, regardless of the origin of the jitter by creating a new stable clock not linked to the source clock by any direct mechanism.
The GMT Clock system operates an intelligent, ultra low jitter, temperature compensated quartz driven clock system with over 28 million selectable frequencies with a precision of better than 0.001Hz(0.005ppm).
- Zero Jitter Mode
When engaged, the GMT system controls the clock that drives the DAC chipsets and takes the data out of the IMS. The GMT Clock is set precisely to match the LONG TERM AVERAGE frequency (digitally calculated) of the incoming clock, so the IMS can never over- or under-flow (which causes highly annoying loud clicks and pops) and does not attempt, nor is forced to track any short term variations (jitter).
Once the GMT Clock has correctly calculated the incoming clock, the rate of updating the DAC's clock with the minimal 0.001Hz step (0.005ppm@192kHz) is at the very least, once every few minutes or so to correct small slow drifts of the source clock, otherwise the clock driving the DACs is completely decoupled from the source.
The Zero Jitter “J” Indicator
The “J” indicator on the front acrylic display of the DP-777 will blink every time the clock is adjusted so it is possible to observe just how stable the clock from the music source is.
As a comparison to the effectiveness of the IMS + GMT system, if the DP-777 used a PLL for clock recovery and applied an equivalent indicator of any adjustment to the clock frequency, the indicator would forever blinking furiously.
This Zero Jitter Mode is available for all digital inputs (SPDIF + USB) and sets the new clock standard for the digital audio world.
Director – Technology
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